Design-Reuse4y
Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR
This equation tells us that the SFDR of the output of the ADC or DAC is the power of the largest clock spur reduced by the ratio between the clock frequency and the largest tone in the output signal.
Design-Reuse10y
An innovative methodology to reduce routing capacitance of ADC channels
Total capacitance on the CS is derived with the following equation: At SoC level, ADC channel gets routed in parallel to each other as shown in figure3a to avoid other net interference with ADC ...