AMD said it has completed its $49 billion acquisition of Xilinx to create the “industry’s high-performance and adaptive computing leader,” marking the largest chip deal in history.

As of the Xilinx Vivado 2020.1 release, the MIPI DSI (display serial interface) and CSI (camera serial interface) IP blocks are now bundled with the IDE to be used freely with Xilinx FPGAs.

CRN dives into the details of the Xilinx deal and what it could mean for the data center and telecom markets, among other things. ‘It’s Not M&A For M&A’s Sake’ In a little over a month ...

It has been discovered that a Sukhoi S-70 Okhotnik-B unmanned combat aerial vehicle (UCAV), found crashed behind Ukrainian lines, was reliant on a plethora of Western chips. The drone included ...

For developers on Xilinx FPGAs they have extended the offer of those two processor cores at zero cost through their DesignStart Programme. It’s free-as-in-beer rather than something that will ...

Ceva-Waves Bluetooth 5.3 dual mode IP is a complete and flexible solution for integration into SoCs/ASSPs. It contains both "classic" BR/EDR Bluetooth and Bluetooth Low Energy and is compatible ...

This SATA Host IP core has been certified for Serial ATA Revision 3.0 compliance on a Xilinx Virtex-6 FPGA by the UNH IOL SATA Consortium in May 2010. ASICS World Services provides a broad line of ...