You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation.

If you had a bunch of these, say up to out999, the delay could be significant. Equivalent Verilog code might look like: always @(posedge clk) begin out1<=ctr1; ctr1<=ctr1+1 ...